1. Field of the Invention
The present invention relates to a data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements.
2. Description of the Prior Art
A data processing apparatus may be arranged to perform a data processing operation on various types of data element. One type of data element which may be subjected to such data processing operations is the floating point data element. A floating point number can be expressed as follows:±1.x*2y
where:                x=fraction        1.x=significand (also known as the mantissa)        y=exponent        
When performing a data processing operation on floating point data elements, a number of eventualities have to be catered for in the processing logic path, and accordingly extra logic needs to be included in the data processing path to perform the required processing dictated by these eventualities (for example rounding, normalization, etc). This often means that the processing path for performing the data processing operation is relatively long, which can have an impact on processing speed. As an example, in a pipelined data processing apparatus used to perform such data processing operations, a relatively large number of pipeline stages may be required to ensure that all of the necessary logic elements required to cover the various eventualities is provided.
For certain data processing operations, for example floating-point addition, it is known to provide within the processing logic different processing paths, each of which is capable of performing the data processing operation under certain conditions. As an example, for floating-point addition, it is known to provide a near processing path and a far processing path, as for example is discussed in the paper “1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features”- by A Naini et al, Proceedings of the 15th IEEE Symposium on Computer Architecture, 2001. The near path can be used if the first and second floating point data elements require at most a 1-bit alignment, whereas otherwise the far path needs to be used. When the input floating point data elements require at most a 1-bit alignment, it is possible that when performing an unlike-signed addition (i.e. equivalent to subtracting one data element from the other) massive cancellation may occur, and to enable the resultant floating point value to be correctly aligned, it is then necessary to provide normalisation logic within the near path. Such logic is not required in the far path. However, in the far path, it is necessary to provide rounding logic due to the fact that the data elements may need more than a 1-bit alignment. Such rounding logic is not required in the near path.
Accordingly, by providing a near path and a far path, the length of each path can be made shorter than would be the case if a single unitary path were provided for performing the data processing operation, and this can hence produce an increase in processing speed. For example, considering the earlier pipelined processing logic example, the pipeline depth can be reduced by using a near path and a far path, which can give rise to increase in processing speed when compared with a unitary processing path. However, one problem that arises when providing more than one processing path for performing the data processing operation is in determining whether the alignment condition required for using any particular path does in fact exist.
In accordance with the technique discussed in the above-mentioned paper from the 15th IEEE Symposium on Computer Arithmetic, prediction logic is used to predict whether the alignment condition for the near path exists, which can make an early prediction as to whether the alignment condition for the near path appears to exist. However, predicted results by their very nature will not necessarily be true, and accordingly it is necessary to perform the processing in both the near path and the far path until such time as the presence of the alignment condition can actually be determined. Hence, whilst the predicted result can be used to perform some initial processing, for example shifting, in the near path, it is not until the actual alignment condition is positively determined that the result from any particular path can be used. Hence, such an approach is not very power efficient, since the data processing operation needs to be performed in both processing paths. Further, this has some impact on the area required for the processing logic, since further logic is needed in addition to the prediction logic to perform the actual detection of the alignment condition at a later stage in the processing path, and to manage the computations being performed within several different processing paths.
A further problem is that because the prediction may be wrong, any assumptions made in an early part of the near processing path based on that prediction cannot be used in the far processing path, since if the prediction proves wrong it will be necessary to rely on the processing performed in the far processing path in order to generate the correct result. Accordingly, there is no opportunity to share logic between the near and far processing paths, which again leads to an implementation which is inefficient in terms of size of the processing logic, and in terms of power consumption.
It is an object of the present invention to provide an improved technique for determining a processing path to be used to perform a data processing operation on input data elements.